Sr. Asic Dft Engineer (silicon)

SpaceX is seeking a Senior ASIC DFT Engineer to implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST. The role involves integration and verification of DFT IPs, setting up and running ATPG tools, and generating patterns for various fault models.

Skills and focus areas

• asic dft
• scan insertion
• compression/decompression logic
• memory bist
• logic bist
• atpg
• stuck-at fault models
• transition fault models
• path delay fault models
• pattern compression
• diagnosis
• hierarchical test flows