Sr. Asic Design Engineer (silicon Engineering)
SpaceX- Location
- Austin, TX
- Work mode
- On-site
- Type
- full time
- Listed
Applications go directly to SpaceX. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
SpaceX is seeking a Sr. RTL Design Engineer for their Silicon Engineering team in Austin, TX. This role involves developing next-generation ASICs for Starlink's satellite constellation and ground infrastructure, focusing on enabling global broadband connectivity. Responsibilities include evaluating architectural trade-offs, implementing RTL, integrating designs, and collaborating with verification and physical implementation teams.
Skills and focus areas
- rtl design
- asic design
- micro-architecture
- verilog
- system verilog
- timing constraints
- physical implementation
- synthesis
- timing closure
- formality check
- cross-disciplinary collaboration
Summary written by Ramai from the original posting. Full details and requirements are on SpaceX’s careers page.
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