Sr. Asic Design Engineer (silicon Engineering)

SpaceX is seeking a Sr. RTL Design Engineer for their Silicon Engineering team in Redmond, Washington. The role involves developing next-generation ASICs for Starlink's satellite and ground infrastructure. Responsibilities include evaluating architectural trade-offs, implementing RTL, integrating designs, and supporting physical implementation.

Skills and focus areas

• asic design
• rtl design
• micro-architecture
• verilog
• system verilog
• timing constraints
• physical implementation
• synthesis
• timing closure
• formality check