Sr. Asic Design Engineer (silicon Engineering)

SpaceX is seeking a Sr. RTL Design Engineer for their Silicon Engineering team in Irvine, California. The role involves developing next-generation ASICs for Starlink's space and ground infrastructure. Responsibilities include evaluating architectural trade-offs, defining micro-architecture, implementing RTL, and collaborating with verification and physical implementation teams.

Skills and focus areas

• asic design
• rtl design
• micro-architecture
• verilog
• system verilog
• timing constraints
• physical implementation
• synthesis
• timing closure
• formality check