[ engineering ]

Silicon Design-for-test (dft) Engineer

Matx

Location
Mountain View, California
Work mode
Remote
Type
full time
Listed
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[ About this role ]

Matx is seeking a Silicon Design-For-Test (DFT) Engineer to implement DFT functions for their AGI compute platform. Responsibilities include designing test solutions for SERDES PHY, performing DFT integration of IP blocks, developing firmware loading flows, and executing block-level DFT insertion and verification.

Skills and focus areas

  • dft implementation
  • serdes phy testing
  • dft integration
  • firmware loading
  • atpg
  • scan chain closure
  • mbist
  • at-speed scan
  • scan compression
  • jtag (ieee 1149.1)
  • ijtag (ieee 1687)
  • streaming scan networks (ssn)

Summary written by Ramai from the original posting. Full details and requirements are on Matx’s careers page.

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