Rtl Design Engineer – Interconnect & Network Datapath

OpenAI is seeking a senior RTL Design Engineer with expertise in interconnect and network datapath for their AI-native silicon organization. The role involves owning the microarchitecture and RTL implementation of on- and off-chip communication components for custom AI accelerators, including NoC fabrics, switches, and networking protocols.

Skills and focus areas

• rtl design
• packet networking
• interconnects
• network datapath
• microarchitecture
• systemverilog
• ethernet switches
• nics
• smartnics
• network accelerators
• rdma/roce
• nocs