Physical Design Engineer - Full Chip Implementation
Etched- Location
- Not specified
- Work mode
- On-site
- Type
- full time
- Listed
Applications go directly to Etched. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
Senior Physical Design Engineer responsible for full-chip implementation, including floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis to GDSII. The role involves leading critical efforts in PPA optimization and timing closure, collaborating with RTL designers, and owning end-to-end physical verification closure.
Skills and focus areas
- physical design
- full-chip implementation
- floorplanning
- place and route (p&r)
- clocking
- timing analysis
- physical verification
- sign-off
- synthesis
- gdsii
- ppa optimization
- timing closure
Summary written by Ramai from the original posting. Full details and requirements are on Etched’s careers page.
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