[ engineering ]

Formal Verification - Dv

Etched
Location
Not specified
Work mode
On-site
Type
full time
Listed
Apply on Etched’s siteFind roles like this with the assistant

Applications go directly to Etched. Ramai takes no fee for placement and no money for ranking.

[ About this role ]

Etched is hiring a Formal Verification Engineer to join their ASIC Design Verification team. The role involves driving formal verification for custom IP, interface IP, and SoC subsystems, working closely with architects, RTL designers, and DV engineers to ensure design correctness and expose bugs.

Skills and focus areas

  • formal verification
  • asic design verification
  • rtl design
  • systemverilog assertions
  • assume-guarantee reasoning
  • abstraction models
  • reference models
  • uvm
  • emulation
  • software/firmware integration

Summary written by Ramai from the original posting. Full details and requirements are on Etched’s careers page.

[ More at Etched ]

See all 123 open roles at Etched →

[ Similar roles at other startups ]

Browse all open engineering roles →

[ Not quite right? ]

Tell the assistant what you’re after — stage, location, stack, visa sponsorship — and it searches every open role for you. A few questions are free, no account needed.

Search with the assistantBrowse similar roles