Dv Intern

Design Verification Intern at Etched, focusing on ensuring the robustness, high-performance, and silicon-readiness of custom IPs for frontier intelligence hardware. Responsibilities include collaborating with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.

Skills and focus areas

• high-speed digital logic
• asic or soc design concepts
• systemverilog
• uvm
• python
• verification
• writing test benches
• physical design flows and tooling
• transformers
• modern artificial intelligence
• ml and llm model architectures
• formal verification