Digital Ic Design Engineer Intern
Neuralink- Location
- South San Francisco, California, United States
- Work mode
- Hybrid
- Type
- full time
- Listed
Applications go directly to Neuralink. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
Digital IC Design Engineer Intern at Neuralink in South San Francisco, California. Responsibilities include micro-architecture design and RTL implementation of low-power digital signal processors, hardware accelerators, GPUs, and radio MAC/PHY. The role also involves designing hardware/software interfaces and optimizing application-specific architectures.
Skills and focus areas
- micro-architecture design
- rtl implementation
- digital signal processors
- hardware accelerators
- graphics processing units
- radio mac/phy
- hardware/software interface design
- firmware
- application-specific architecture optimization
- system modeling
- workload analysis
- architecture-level design trade-offs
Summary written by Ramai from the original posting. Full details and requirements are on Neuralink’s careers page.
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