[ engineering ]

Dft Intern

Etched
Location
Not specified
Work mode
On-site
Type
intern
Listed
Apply on Etched’s siteFind roles like this with the assistant

Applications go directly to Etched. Ramai takes no fee for placement and no money for ranking.

[ About this role ]

DFT Intern at Etched. This role involves reviewing and refining DFT flow automation for chip-level regression, contributing to DFT verification (MBIST, Scan, BSCAN, SSN simulations), and developing flows for ATPG fault models. The internship is available for Summer '26, Fall '26, Spring '27, and Summer '27.

Skills and focus areas

  • electrical engineering
  • computer engineering
  • hardware description language
  • asic design
  • soc design
  • digital logic design
  • asic design flow
  • synthesis
  • sta
  • dft
  • scripting
  • python

Summary written by Ramai from the original posting. Full details and requirements are on Etched’s careers page.

[ More at Etched ]

See all 123 open roles at Etched →

[ Similar roles at other startups ]

Browse all open engineering roles →

[ Not quite right? ]

Tell the assistant what you’re after — stage, location, stack, visa sponsorship — and it searches every open role for you. A few questions are free, no account needed.

Search with the assistantBrowse similar roles