[ engineering ]
Dft (design for Test) Engineer
Etched- Location
- Not specified
- Work mode
- On-site
- Type
- full time
- Listed
Applications go directly to Etched. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
Design for Testability (DFT) Engineer responsible for ensuring the testability of integrated circuits (ICs) from design to production. This role involves developing and implementing DFT architectures, integrating methodologies like scan insertion and BIST, and collaborating with design teams to improve test coverage and silicon reliability.
Skills and focus areas
- design for testability (dft)
- asic
- soc
- scan insertion
- boundary scan
- built-in self-test (bist)
- memory bist (mbist)
- verification
- simulation
- formal verification
- silicon debug
- failure analysis
Summary written by Ramai from the original posting. Full details and requirements are on Etched’s careers page.
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