[ engineering ]
Design Verification Engineer - Interface Ip
Etched- Location
- Not specified
- Work mode
- On-site
- Type
- full time
- Listed
Applications go directly to Etched. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
Etched is seeking a Senior Design Verification Engineer for their Interface IP DV team. This role involves end-to-end ownership of IP subsystems like PCIe, Ethernet, and CPU, developing UVM/SystemVerilog verification environments, and collaborating with integration teams to ensure hardware-software stack correctness and performance.
Skills and focus areas
- design verification
- ip subsystems
- pcie
- ethernet
- cpu verification
- low power peripherals
- sensors
- vendor ip configuration
- uvm
- systemverilog
- hardware-software stack validation
- coverage closure
Summary written by Ramai from the original posting. Full details and requirements are on Etched’s careers page.
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