Asic/soc Silicon Verification Engineer

MatX is seeking an Asic/soc Silicon Verification Engineer in Mountain View, California. The role involves contributing to verification methodology, owning verification execution at subsystem and chip-level, and planning/driving verification reviews. Candidates should have concept-to-silicon experience and proficiency in SystemVerilog, Python, C/C++, and UVM.

Skills and focus areas

• verification methodology
• testbench development
• functional coverage
• structural coverage
• verification test plans
• silicon verification
• systemverilog
• python
• c/c++
• bluespec
• uvm
• assertion-based verification (abv)