Asic/soc Silicon Physical Design Engineer

Matx is seeking a Senior ASIC/SoC Silicon Physical Design Engineer in Mountain View, California. This role involves contributing to physical design methodology, owning physical design deliverables from RTL to GDSII, and collaborating with cross-functional teams to achieve optimal PPA results for high-performance GenAI silicon.

Skills and focus areas

• asic physical design
• soc silicon physical design
• rtl to gdsii
• floorplanning
• synthesis
• place & route
• clocking
• equivalency verification
• extraction
• timing analysis
• power estimation
• emir