[ engineering ]
Asic/soc Dft Engineer (silicon Engineering)
SpaceX- Location
- Palo Alto, California
- Work mode
- On-site
- Type
- full time
- Listed
Applications go directly to SpaceX. Ramai takes no fee for placement and no money for ranking.
[ About this role ]
SpaceX is seeking an ASIC/SOC DFT Engineer to develop next-generation ASICs for Starlink's space and ground infrastructure. Responsibilities include evaluating design readiness for scan insertion, integrating DFT fabrics, and running ATPG analysis for scan chain construction and coverage.
Skills and focus areas
- design for test (dft)
- scan insertion
- automatic test pattern generation (atpg)
- rtl
- physical design
- synthesis
- problem-solving
- collaboration
Summary written by Ramai from the original posting. Full details and requirements are on SpaceX’s careers page.
[ More at SpaceX ]
See all 2874 open roles at SpaceX →[ Similar roles at other startups ]
Browse all open engineering roles →[ Not quite right? ]
Tell the assistant what you’re after — stage, location, stack, visa sponsorship — and it searches every open role for you. A few questions are free, no account needed.